1. Technical Field
This invention relates generally to resistive memory devices, and more particularly, to a method of fabricating oxide layers of such a device.
2. Background Art
FIG. 1 illustrates a type of two-terminal memory device 30. The memory device 30 includes a metal electrode 32, an active, for example metal oxide layer 34 on the electrode 32, and a metal electrode 36 on the layer 34. Initially, and with reference to FIG. 2, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an on-state resistance.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the layer 34 (and memory device 30) in a high-resistance or substantially non-conductive state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
It may be desirable to vary the configuration of a memory device of this type in order to vary the operating characteristics thereof. For example, the device 40 as shown in FIG. 3 includes a second metal oxide layer 46 of thickness A on the oxide layer 44 of thickness B (metal of oxide layer 46 selected as different from metal of oxide layer 44), along with electrode 42 and electrode 48. Inclusion of this second metal oxide layer 46, and selection of the thicknesses of the oxide layers 44, 46, can provide variation of the operating characteristics of such a device 40, for example varying the programming and erase characteristics of the device 40 as desired. However, fabrication of such a device 40 has been problematical, as will now be shown and described.
Initially, it is assumed that a device with a layer thickness A and a layer thickness B is to be achieved (FIG. 3), as selected by the fabricator of the device. With reference to FIG. 4, a metal electrode 50 is provided. A metal layer 52 (different from the metal of electrode 50) is deposited on the electrode 50. This metal is of a selected thickness C so that upon complete oxidation of the entire layer 52, at elevated temperature and in the presence of an oxidizing agent such as O2, it would be expected that a resulting oxide layer of thickness A would result, as one skilled in the art would realize. That is to say, one can predict and expect the thickness A when the metal layer of thickness C is fully converted to oxide. However, it has been found that because of the high temperature involved in the oxidation process, metal of the layer 52 will alloy with the metal of electrode 50 during this oxidation process, forming the alloy layer 54. FIG. 5 illustrates partial oxidation 60 of the metal layer 52 and formation of the alloy layer 54 between the metal layer 52 and electrode 50. This alloying reduces the amount of metal in the layer 52 which can be oxidized. Further oxidation increases the thickness of the alloy layer 54, reducing even further the amount of metal that can be oxidized, so that upon full oxidation of the remaining metal layer 52 (down to the alloy layer 54, FIG. 6), the thickness D of the oxide layer 60 is much less than the target, desired thickness A.
Further oxidation causes the alloy layer 54 to oxidize, forming an alloy oxide layer 64 (FIG. 7), the presence of which is not desired. The oxidation process may be continued to oxidize a portion 66 of the electrode 50 to the desired thickness B (FIG. 8). Electrode 68 is then provided on the oxide layer 60, resulting in the device 70 (FIG. 9).
It will be seen that the resulting structure includes an incorrect thickness of the oxide layer 60, along with an undesired alloy oxide layer 64.
What is needed is a process which provides that the desired configuration of device is achieved.